1. Field of the Invention
The present invention relates to a stack structure of semiconductor packages and the manufacturing method thereof, and more particularly, to a stack structure of semiconductor packages and the manufacturing method thereof which utilize connectors as the electrical connection structure.
2. Description of the Prior Art
Along with the rapid progress of the computer and internet communication, the semiconductor products need to be multi-functional, portable, light, thin, and small-sized to satisfy the customers' demand. Therefore, the industry of chip package has to develop towards the high accurate processes to comply with the requirements of high-power, high-density, lightness, thinness, compactness and mini-size. In addition, the electronics packaging also needs to have the features including high reliability and good thermal dissipation to transmit signals and provide electrical power, and provide effective routes for thermal dissipation, structural protection and support.
Presently, the three-dimensional (3-D) package may be classified into two categories, the Package on Package (PoP) and the Package in Package (PiP). The PoP is a typical 3-D package, which utilizes the process technology to stack two independent completed packages. In the other way, PiP utilizes a spacer to stack a single package without mounting solder balls onto a chip and then package them together using the Epoxy Molding Compound (EMC). Because the PoP utilizes the method of the Surface Mount Technology (SMT) to stack two independent packages which have been packaged and tested, it may reduce the process risk and so as to promote the product yield.
Please refer to FIG. 1A and FIG. 1B, FIG. 1A and FIG. 1B are a solid schematic diagram and a cross-sectional schematic diagram for the manufacturing process of a conventional PoP package. A Printed Circuit Board (PCB) spacer 30 is set between the electrical connections of the carrier plates for two packages 10, 20, and the SMT method is utilized to fuse the two packages 10, 20. Because the conductive terminals 32 on the PCB spacer 30 have to be set one on one corresponding to the terminals 12, 22 on the carrier plate of the packages 10, 20, the inaccurate alignment and the bad connection between the materials are two possible problems. Additionally, a warpage phenomenon may be induced by the different Thermal Expansion Coefficients (TECs) of the different materials, and the bad connection may further lead to a popcorn phenomenon.